As you will see, every register is 8 bits in size, with every bit being a different setting.

Now these bits don't really mean anything when you look at them like this, so we need to load the pcr file that holds the descriptions for the via chipsets.

To do this go to the File menu at the top of the program and you will see an option PCR Open shown below.

You will then need to load the file AMD762.PCR that should be in the directory with WPCREDIT.

It will give an error message saying that the Vender ID differs, just hit continue

Register 46

Speculative Read Data Movement Enable

In two processor systems read data commands are returned speculatively before the probe response is received. This setting changes how long after the probe is send before this action is taken. This setting uses all 8 bits in register 46 and both CPUs will need to have the same setting.

0000=disabled
0001=single clock
0010= 2 clocks
1111=15 clocks

Register 49

ECC

4 is ECC Diagnostic Mode
0 Disables ECC and 1 Enables it

3,2 Configure what all will be checked and corrected.
00 for this if Bit 4 is set for disabled.
01 Errors are checked for but NOT corrected
10 has some error correction but doesn't take full advantage of data integrity checking
11 This is everything that ECC can possibly offer

Memory Performance

Register 54

1,0 = TRCD RAS to CAS delay 11=4 cycles 10=3 cycles(default) 01=2 cycles 00=1 cycle

3,2 = CAS Latency 01=2 cycles 10=2.5 cycles 00=3 cycles

6,5,4 = TRAS 111=9 cycles 110=8 cycles 101=7 cycles(recomended) 100=6 cycles 011=5 cycles 010=4 cycles 001=3 cycles 000=2 cycles

This next one wants to be tricky. It spans across two different registers ;) Register 54 AND 55 both you'll have to go to for this setting.

54:7 + 55:0 =TRP(see bit 8) 00=3 cycles(recomended) 11=4

cycles

Register 55

3,2,1 TRC 111=10 cyc 110=9 cyc 101=8 cyc 100=7 cyc 011=6 cyc 010=5 cyc 001=4 cyc 000=3 cyc

7,6 Page Hit Limit 00=1 cycle 01=4 cycles 10=8 cycles 11=16 cycles