Register 56
2,1,0 = Idle Cycle Limit 111=disable 110=48 cyc 101=32 cyc 100=24 cyc 011=16 cyc 010=12 cyc 001=8 cycles(suggested) 000=0 cycles
Register 57
7 = Super Bypass Wait State 0=100Mhz FSB 1=133Mhz FSB
2 = Write to read Delay 0=1 cyc 1=2 cyc
1,0 = Write Recovery Time 00=1 Clock cyc 10=2 Clock cyc 11=3 Clock cyc
Register 5A
4 = Burst Refresh Enable 0=no refresh 1=Refresh Refreshes are only queued during long sequences of operation to the same memory device. When enabled the 762 will queue up to four refreshes before issuing.
1,0 = Cycles Per Refresh This is something that I simply couldn't write into the PCR file due to the variances in system buses and their resulting numbers. Please notice that 66 is half the speed as 133 and therefore the time values are exactly doubled. If you were to increase your bus speed 25% the resulting number will be 25% lower.
Register 61
1 = Super Bypass Enable 0=disabled 1=enabled
That means that all you SMP guys won't be able to see the benefits of Super Bypass
PCI Bus tweaks
Register 71
2 = PCI Pipe enable 0=disabled 1=enabled
1 = PCI Block Write Enable 0=disabled 1=enabled
Register 84
2 = AGP Prefetch Enable 0=disabled 1=enabled
This enables the system controller to prefetch data from the RAM when a PCI master on the AGP bus reads from the main memory
1 = PCI Prefetch Enable 0=disabled 1=enabled
This enables the system controller to prefetch data from the RAM when a PCI master on the PCI bus reads from the main memory
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