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X58 & ICH10 North & South bridge for the Core i7

The new Core i7 processors needed a new chipset to support them. Unlike previous Intel chipsets, there was no need to provide a memory controller in the Northbridge, and the connection to the processor now was via a QPI interconnect instead of a front side bus.

The HyperTransport like interconnect consists of two sixteen bit lanes unidirectional lanes. By having lanes for each direction of transfer there is no need to waste time switching directions, and it also eliminates the possibility of conflict by having the processor and chipset trying to drive a bus at the same time.

The Core i7 920 and 940 run the QPI at 4.8GT/sec, which translates to potentially 9.6GB/sec in each direction for an aggregate potential bandwidth of 19.2GB/sec per QPI link. The Core i7 965 Extreme runs the QPI paths at 6.4GT/sec, with a potential for a staggering 25.6GB/sec of theoretical maximum aggregate bandwidth per link - MUCH faster than the old FSB design of Core 2 and older generations.

As you can see on the diagram below, a Core i7 processor connects to three channels of DDR3 memory (at up to 8.5GB/sec per channel with DDR3-1067) and has a QPI link to the X58 Northbridge (now called an IOH for I/O Hub).

The X58 provides up to 36 lanes of PCIe 2.0, which can be used to support multiple different configurations of slots - however I suspect one popular configuration will be two PCIe 16x slots and several 1x slots.

The X58 also connects to the new ICH10 or ICH10R Southbridge over a 2GB/sec DMI link.

ICH10 provides:

• 12 USB 2.0 High speed ports
• 6 PCIe 1x slots
• Integrated 10/100/1000Mbps Ethernet
• Intel High Definition Audio
• Six SATAII ports with optional Intel Matrix Storage (RAID) and Turbo Memory (flash drive cache)
• BIOS support
• Intel Extreme Tuning support

Here is the diagram:

Of course, you will find the X58 on Intel's new DX58SO motherboard, which we will describe in more detail later.