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Phenom II Update: The Next Core Revision - PAGE 1
Carl Poirier - Wednesday, November 4th, 2009

 

Finally, the next core revision from AMD is here. I can say I was very eager to for it to be released. Most of the time, the enthusiast community is expecting slightly better overclocking performance from new core revisions. Think of the DO stepping of the Core i7 920; Overall it seems people were not deceived by this expected stepping. However, we have also seen the inverse. Many enthusiasts buying a Q6600 got a later stepping that quite frankly was far from reaching the same clocks as the first ones. They seemed to max around 3.2 to 3.4Ghz on air, where the first ones could reach up to 4GHz. People thanked Intel very much.

So on which side will the new C3 revision from AMD be? For the better or worst? Looking at the specs, my first impressions are that it will be for the better. A little while ago, we took a look at the Phenom II X4 965 Black Edition, a 3.4Ghz unlocked quad-core that featured a 140W TDP and a much higher stock core voltage; 1.40V instead of 1.35V.  Altough it overclocked much higher than its little brother the 955, it would have been great to stay within the 125W thermal enveloppe. Well, it has now been achieved. The unit we will look at today is a brand new Phenom II X4 965, but on the new core revision. It shares the same price as the older revision, which by the way has been lowered to $195 USD.

This time, it won't be a traditional processor review, since the performance has not been altered. Instead, I will focus on the main improvements of the new revision. Let's first take a look at the complete specifications table. I have highlighted the differences with the previous 965.

Specifications

Model Number & Core Frequency
X4 965 Black Edition = 3.4GHz
X4 955 Black Edition OPN

HDZ965FBK4DGM (“M” indicates new revision)

L1 Cache Sizes

64K of L1 instruction and 64K of L1 data cache per core (512KB total L1 per processor)

L2 Cache Sizes

512KB of L2 data cache per core (2MB total L2 per processor)

L3 Cache Size
6MB (shared)
Total Cache (L2+L3)
8MB
Memory Controller Type
Integrated 128-bit wide memory controller
Memory Controller Speed
Up to 2.0GHz with Dual Dynamic Power Management
Types of Memory Supported

Unregistered DIMMs up to PC2-8500 (DDR2-1066MHz) -AND- 4 DIMMs at PC3-10600 (DDR3-1333MHz)

HyperTransport 3.0 Specification

One 16-bit/16-bit link @ up to 4.0GHz full duplex (2.0GHz x2)

Total Processor-to-System Bandwidth

Up to 37.3GB/s total bandwidth [Up to 21.3 GB/s memory bandwidth (DDR3-1333) + 16.0GB/s (HT3)]

Up to 33.1GB/s total bandwidth [Up to 17.1 GB/s memory bandwidth (DDR2-1066) + 16.0GB/s (HT3)]

Packaging

Socket AM3 938-pin organic micro pin grid array (micro-PGA)

Fab location

GLOBALFOUNDARIES Fab 1 module 1 in Dresden, Germany (formerly AMD Fab 36)

Process Technology

45-nanometer DSL SOI (silicon-on-insulator) technology

Approximate Die Size
258 mm2
Approximate Transistor count
~ 758 million
Max Temp
62o Celsius
C1E Support

Hardware implemented

Nominal Voltage
0.825-1.4V
Max TDP
125 Watts

As you can see, not much has changed, but it does seem to be for the better. I want to put emphasis on the fact that it now supports four DIMMs at 1333MHz officially instead of two, so it looks like the memory controller has been upgraded.

 


Article Index

1.A few improvements
2.Test Setup & Benchmarks used
3.Overclocking the memory sub-system
4.Memory sub-system benchmarks: part 1
5.Memory sub-system benchmarks: part 2
6.Memory sub-system benchmarks: part 3
7.Overclocking the processor cores
8.Processor benchmarks: part 1
9.Processor benchmarks: part 2
10.Power Usage & Conclusion

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